1. Field
Example embodiments relate to methods of fabricating a semiconductor device. Other example embodiments relate to methods of fabricating a semiconductor device including a contact structure.
2. Description of the Related Art
There has been a desire to increase the integration density of semiconductor devices in order to form finer patterns. Photolithographic processes necessary for forming finer patterns are reaching technical limits. For example, process margins required for a contact structure formed through an interlayer insulating layer are becoming smaller due to the downscaling of a contact structure and a reduction of an interval between contact structures. Conventional photolithographic limitations make it difficult to form a contact structure with finer patterns.
The conventional art acknowledges a method of forming a spacer-type material layer pattern. The method may be used to form protruding finer patterns. It is difficult to form a contact structure using the conventional method of forming a space-type material layer pattern.
The conventional art also acknowledges a method of forming a fine pattern using a double mask layer. In this method, a difference in pattern density between a high-density pattern region and a low-density pattern region may be problematic. For example, subsequent planarization process(es) may be performed at different rates depending on the pattern density such that a step is generated in the contact structure. The reliability of interconnection lines may deteriorate due to the step of the contact structure.